1. Field of the Invention
The present invention relates to a ferroelectric semiconductor memory using a ferroelectric capacitor. In particular, the present invention relates to a ferroelectric semiconductor memory having a reference potential generating circuit which generates a reference potential used when data is sensed by a sense amplifier circuit.
2. Description of the Related Art
As non-volatile semiconductor memories, known are ferroelectric random access memories (FeRAM) using a ferroelectric capacitor. In FeRAMs, one memory cell is formed of a selection transistor which is connected at one end to a bit line, and a ferroelectric capacitor which is connected between the other end of the selection transistor and a plate line.
In FeRAMs, data “1” or data “0” is stored according to the polarization direction of the ferroelectric capacitor. Suppose that data “1” is written in the memory cell, if a potential of the plate line is increased when the selection transistor is in an ON state and the memory cell is selected, the amount of electric charge flowing from the ferroelectric capacitor into the bit line increases, and a potential of the bit line greatly rises. In the meantime, suppose that data “0” is written in the memory cell, if the potential of the plate line is increased when the memory cell is selected, the amount of electric charge flowing from the ferroelectric capacitor into the bit line is smaller than that in the case of data “1”, and rise in potential of the bit line is smaller than in the case of data “1”. When data is read from a memory cell, the sense amplifier circuit compares the magnitude of the potential of the bit line with that of the reference bit line, and determines whether the read data is “1” or “0”, on the basis of the comparison result. The reference bit line is supplied with a reference potential which has an intermediate value between the above two potentials of the bit line.
Various types have been proposed as a reference potential generating circuit which generates the reference potential. Among them, there is a type in which a memory cell whose a ferroelectric capacitor is replaced by a paraelectric capacitor is used as the reference potential generating circuit. The selection transistor is connected at one end to the reference bit line, and the paraelectric capacitor is connected between the other end of the selection transistor and a dummy plate line.
The following is the reason why a paraelectric capacitor is used for the reference potential generating circuit, not a ferroelectric capacitor as used in the memory cell. Ferroelectric capacitors cannot stably generate a reference potential for the following defects: ferroelectric capacitors greatly vary in capacitance; ferroelectric capacitors fatigue through polarization inversion and capacitance change; capacitance of ferroelectric capacitors reduces through polarization; and imprint is caused to change the property thereof.
In the reference potential generating circuit having the above structure, when the potential of the dummy plate line is raised from 0V to VDC, the potential of the reference bit line rises. The capacitance of the paraelectric capacitor and the value of the VDC are controlled such that the potential of the reference bit line obtained by this rise becomes a desired reference potential.
However the area of the paraelectric capacitor causes problems. Generally, an MOS structure is used for paraelectric capacitors. The gate insulating film material of MOS structure has a very small dielectric constant being 1/100 to 1/1000 of that of a ferroelectric capacitor. Therefore, to obtain a reference potential of a certain value or more, it is necessary to greatly increase the area of the paraelectric capacitor and consequently the area occupied by the reference potential generating circuit. This increases the area of the chip.
A reference potential generating circuit comprising a paraelectric capacitor and a selection transistor is disclosed in, for example, Jpn. Pat. Appln. KOKAI Pub. No. 2002-83493 (FIG. 18).